A. Technical Field
This invention relates generally to electro-magnetic induction and interference, and more particularly, to the design of inductor coil elements within a semiconductor device.
B. Background of the Invention
Technological advancements in semiconductor manufacturing and electronic circuit design have resulted in a continual increase of component density within electrical circuits. These improvements in component density have resulted in a more efficient use of silicon area within the chip and a lower cost of production for each chip.
As the proximity of electrical components increases, the affects of electrical cross-coupling or crosstalk may significantly degrade the performance of the circuit. The impact of electrical cross-coupling is a more significant issue in circuits that are operating at high frequencies. Oftentimes, these high speed circuits need to be specifically designed to address interference and cross-coupling in order to comply with electro-magnetic compatibility (“EMC”) requirements.
The design and placement of electrical components, such as inductors, within a circuit may significantly affect the electro-magnetic emission from a circuit and the cross-coupling therein. For example, inductors that are sufficiently proximate to each other may reduce the electrical performance of each other through parasitic mutual inductance. In particular, inductor coils produce external magnetic fields that can modify electrical characteristics, such as voltage or current responses, of other inductor coils. In order to reduce the amount of inductor cross-coupling, circuit designers have been forced to provide a sufficient distance between inductor coils so that electro-magnetic interference between the coils is reduced.
FIG. 1 illustrates this electro-magnetic interaction between to proximate inductor coils. As shown, a first inductor L1 102 and a second inductor L2 104 are located sufficiently close to each other so that cross-coupling occurs. The polarity of the inductors, L1 102 and L2 104, are shown such that the polarities are symmetrical and current is flowing through the inductors in the same direction. In particular, current I1 112 in the first inductor L1 102 is flowing in the same direction or substantially similar direction as current I2 114 flowing in the second inductor L2 104.
The magnetic field produced in the first inductor L1 102 interferes with the magnetic field produced in the second inductor L2 104 resulting in magnetic field interference between the two inductors. This interference may be constructive resulting in larger magnitude magnetic fields. As a result of this interference, the first current I1 112 in the first inductor L1 102 and the second current I2 114 in the second inductor L2 104 are undesirably affected by the interference. As one of the currents changes, the electro-magnetic fields change and affect the other current accordingly.
Circuits having multiple inductors must properly address this electro-magnetic interference, or cross-coupling, so that the circuit functions consistently and properly. FIG. 2 illustrates an exemplary differential low noise amplifier (“DLNA”) in which inductor interference can potentially be an issue. Inductors Ld1 202 and Ld2 204 are required to be separated by a minimum distance within the semiconductor so that interference falls within a tolerable range. Inductors in series may also be affected by each other when in close proximity. Source inductors Ls1 207a and Ls2 207b share common node and are therefore required to be kept close to the differential FET 209a and 209b. Such restriction makes the placement of the inductors difficult to implement on chip.
One skilled in the art will recognize that the circuit design, including the inductor values and location within the semiconductor, is designed in accordance with a “far resonance” configuration. Other design configurations may also be employed to sufficiently reduce inductor parasitic cross inductance between components therein. These constraints may reduce the component density within circuits as well as present constraints in the design and implementation of various circuits.